vhd2vl

[For readability, moderator comments have been removed, as well as minor questions for better understanding.]

Thanks so much for inviting me. It's a pleasure to rub shoulders with so many smart people. And while this community knows me for vhd2vl, at least some of you might, that my primary focus is really using FPGAs and all these open source toolchains to do DSP for particle accelerators. So this is a hobby project of mine, but I'm glad some people find it useful, and yeah.

So I want to tell you what vhd2vl is, for those of you who don't already know where it came from, how it fits into the general toolkit, and what does it tell us about code. I think it's kind of interesting, actually. In summary, it converts VHDL to Verilog, at least some dialects of VHDL. It's up on GitHub. It's licensed under GPLv2. And I want to point out that this question, "Can I convert VHDL code to Verilog?", keeps coming up. Maybe not enough to call it frequent, but if you go back in the records and scan forums, and Google is actually great at this, you can find questions going back a long time. It keeps coming up. And every time it pops up, the immediate question is, "Why do you want to do that?" Well, people have their reasons. And then the second immediate answer is "No." And then eventually somebody says, "Try some proprietary program, maybe it'll work." And then, varying on that, "Try synthesizing with Vivado or Quartus or something, and then you can usually, you can get that to re-emit the consequences of its synthesis into some portable form like Verilog." But always this comes with a caveat that any results you get will be totally, well, maybe not totally, but probably useless for maintenance.

You can find, at least, I had trouble last night finding any tables that show the corresponding syntax, right? They're both hardware description language, at least when you go to the synthesis subset. So this is how you say "and" in Verilog, here's how you say "and" in VHDL, here's how you create a loop in Verilog, here's how you do it, right? It's the same. You're doing the same stuff just with different syntactic sugar. So you'd say, well, if I have a short program and maybe I'm not an expert in VHDL or Verilog, you should be an expert in one or the other. But if I have it in one form, I should be able to follow the rules and convert it to the other thing. But that's what computers are for.

So in 2003, Vincenzo posted his answer to a programming forum and says, "I wrote a translator that supports a limited but useful subset of synthesizable VHDL. Blah, blah, blah. Since we have no commercial interest in such software, I decided to release it under GPL". So he did it. So that's vhd2vl, at least the first version. So he's actually based in Australia and he really didn't do much maintenance on that for a while, after the first couple of years. So I found it useful. I was using it and I saw problems with it. So it is open source, so I started contributing back. And that has made me the maintainer since 2005. I got some help from Alejandro, sorry, from Rodrigo in Argentina, starting like six years ago. That's been very helpful.

So now that we have vhd2vl, now the real answer is, wrong answer, okay, real answer is forum posters still don't know about it. So they still post their obsolete answers. If you find VHDL written by pragmatic hardware engineers, that usually works just fine with this code. If you get some software designer who's enamored with the high-level features of VHDL, maybe that won't work so well. And this is really coming out of the Unix paradigm. It's based on, right, it's just a Unix program. So I assume there are some Windows users out there. If you can run vhd2vl under WSL, what's called Windows Subsystem for Linux, send me an email and I can say now it's a Windows program too. There are other recipes and programs out there. I found one written in Java, but it's apparently free to download if you give your email and some other information. It's definitely not open source. People use GHDL for this purpose. Icarus Verilog made an attempt to do this so they could parse VHDL, but that's now abandoned and I'm pretty sure marked as deprecated.

And there was that comment before that any result would be totally unreadable. I hope the font size lets you look at this. And I hope, so the left, this is one particular example in our test set for our code base. The left side is bog standard description of a counter or a frequency divider in VHDL that I've forgotten the provenance of, but it works. And if you use vhd2vl on it, you get the Verilog on the right. Took some really, really small edits to get it to squash onto the page here. I took out a couple of new lines. But I hope you find that the right-hand side is perfectly legible and in fact even most of the comments are preserved. In some contexts, that's actually a real killer feature. So it's not that it's, I mean, the machine generation side is good and it's pretty, it's accurate. If it fails, it fails at the parsing step, not at the, not by generating wrong code. But the result is actually legible. So you could actually import that into a pure Verilog code base. Hello.

And I think this calls into focus some comments about what a program really is. And the ability, so once you write down a program in your text editor, it has a life of its own. This is why we license code. So it can go on and be reused. But this forces you to manipulate your program with other programs. So you write your Verilog and you translate it. You compile it. You synthesize it. You lint it. You write your VHDL. You compile it. You translate it. You lint it. You store it in your Git repository. Having links between all of these parts of the chain is crucially important. This is, the tools to do this, to manipulate programs, range from outlandishly complex like GCC to really simple, right? If I have said that I can start making bulk changes to the program to meet my changing needs. And vhd2vl is just one more program in that suite of tools to manipulate other programs. And I want to point out that tools like this are useless unless people can picture what they do and apply them productively. And it's easy, at least for some audiences, like the people in this room, to say, if you have VHDL and you want Verilog, grab vhd2vl and it should do a pretty good job for you. Try it, right? Don't assume it will work until you verify it empirically.

But it's a tool. Kind of out of the Unix paradigm from the 1970s. And I want to, I hear a lot about AI at this workshop, at this conference. It's not obvious to me that AI means anything in this regime. We value tools that are reproducible, regression testable. I don't see any sense that AI is going to be in that category. Maybe it can be a mechanism to help find bugs. We've done fuzzing for a long time to look for bugs in software. Maybe AI will help us find our bugs. But then we need to turn it into an actual test. I missed, wait, wait, wait, wait, hmm, I jumped across a couple [slides] here.

So I want to, I want to compare vhd2vl with a couple of other programs and this is why I say that I'm lucky to rub shoulders with such brilliant people in this room. It's a tiny fraction, tiny fraction of the size of some of these other programs. And we have, I counted six contributors, two current. This is a far cry from what these other tools are. Internally, vhd2vl uses Flex and Bison, but a third of it is actually just standard C99. So it's not a big program, but it's a useful program. Yeah, I wanted to get this.

What is a program? I said that here. But kind of the introduction to that, data is code. Buffer exploit writers know that. Code is speech. There's a US Supreme Court decision that validates that. And code is data. So being able to use code as data, this is the innovation from Grace Hopper and kind of building on John von Neumann, that computers, programming computers is a real thing. And that's where, right, that's what takes software and makes it an investment instead of a one-time use punch card drawing equations on a piece of paper.

So all I want to really say is that vhd2vl can play a role in putting code to work in new ways. Of course, I'm eager to get successes and bug reports. I want to end with one little comment here. I have a few seconds. I think it's really intriguing that I get to give this talk in Antwerp, where when I walk down the street, businesses don't care what language they give you their information in. It could be French or German or Flemish or English. They don't care. And people can cope. Historically, computers haven't really coped well with multi-language input. So vhd2vl is maybe a very small piece, but I think it's a constructive piece in this world where you can't assume that everything is uniform. So, dank u wel.

Q&A

1. What's the boundary between what will work and what won't work, and how does the user know when it works or not?

   There is, well, I mean, you can read the README, and there are about ten points to watch for. And then in the end, you just try it and see if it crashes or gives you a useful result.

2. Is there some quantitative issue?

   Straight register transfer level is good. Generate loops, or whatever VHDL calls them. I'm a Verilog guy, not a VHDL guy. So, yeah. Complicated things. What do you call them? I forget the...

3. The second part of my question, how does the user know when it works or not?

   Oh, if it errors out, then it didn't work. If it produces output, it's supposed to be correct.

4. So, this is going to be a naive one, but is there more of a need for a VHDL to Verilog versus a Verilog to VHDL, and any comments along those lines? It seems very one-dimensional.

   Yeah, this is one-directional. I commented that I think Icarus Verilog can do Verilog to VHDL. It won't preserve comments, but I think it's pretty readable output.

5. I should ask a slightly annoying question. What happens to the assert statement at the end of your code example? The big code example you have in the VHDL, the assert, and the second to last line, I don't see it in there.

   Yep. No, it doesn't understand asserts. I mean, an assert is not synthesizable. So, we're doing the synthesizable subset. So, for non-synthesizable things, it would produce... The best scenario is it ignores it, right?

6. Is there a parsing case for the code? Is there any case for the boundaries of the codes? And asserts and lines, you can process?

   It can process assert, but it ignores them. Again, for details like this, you should really look at the... I mean, there's a line by line, right? These are the things to watch out for in the README. It's not that long, right? It's not a textbook. It's like two pages long in the README, including a checklist of things that it can and cannot do. Little things like VHDL is case insensitive and Verilog is case sensitive. So, this program is case retentive. And that could trip people up.

7. This seems like a big job to achieve this translation. Can you give me some use cases? Like, why were you...

   It's 3,000 lines of code. It's not a big deal.

8. Why did you have to drive to want to translate VHDL into Verilog?

   Oh. I was working on a collaborative project where I wanted to write Verilog and one of my co-workers wanted to write VHDL. So, we found a way to just make it work.

9. You're a Verilog guy. You try to turn everything into Verilog...

   Well, and at least at the time of that writing, GHDL was very immature and Icarus Verilog worked really well.