Congratulations!
We are very happy to announce the list of papers accepted for presentation at OSDA 2023!
| Authors | Title |
|---|---|
| Davide Cieri, Nicolò Vladi Biesuz, Rimsky Alejandro Rojas Caballero, Francesco Gonnella, Nico Giangiacomi, Guillermo Loustau De Linares and Andrew Peck | Hog 2023.1: a collaborative management tool to handle Git-based HDL repository |
| Lucas Klemmer and Daniel Grosse | Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV |
| Vamsi Vytla and Larry Doolittle | Newad: A register map automation tool for Verilog |
| Frans Skarman and Oscar Gustafsson | Spade: An Expression-Based HDL With Pipelines |
| Stefan Riesenberger and Christian Krieg | Towards Power Characterization of FPGA Architectures To Enable Open-Source Power Estimation Using Micro-Benchmarks |
We would like to say "thank you" to all authors who submitted their papers! It was a tough selection process, so if it did not work out this year, please consider submitting to OSDA again in the future!
Poster Presenters
Besides our rich program of invited speakers, OSDA gives newcomers the opportunity to present their work to a highly prestigious forum of experts. Of course, the workshop is also an excellent environment to address a broader range of interested delegates from industry and academia. Poster presenters successfully submitted their work to a rigorous review process. Congratulations! Meet them during the coffee break at their posters! The list of presenters is given in alphabetical order.
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Christian Krieg
Post-Doctoral Researcher and Teacher at TU Wien -
Daniel Grosse
Full professor at Johannes Kepler University Linz & DFKI Bremen -
Francesco Gonnella
Senior Firmware Engineer at University of Birmingham -
Lucas Klemmer
PhD Student at Johannes Kepler University Linz -
Oscar Gustafsson
Associate Professor at Linköping University -
Stefan Riesenberger
Master Student at TU Wien (Vienna University of Technology) -
Vamsi Vytla
Electronics Engineer at Lawrence Berkeley National Lab
Christian Krieg
Post-Doctoral Researcher and Teacher at TU Wien
Christian is a post-doctoral researcher and teacher at the Insitute of Computer Technology, TU Wien, Vienna, Austria. Christian is very happy about the availability of open-source design automation tools, because they provide so much insight into the mechanics that turn an idea into a working product. He heavily uses open-source design automation tools in his research, and has contributed to pyosys, the Python-bindings for Yosys. In 2016, Christian received the ICCAD William J McCalla Best Paper Award (front-end category). Christian teaches a digital design class, completely backed by open-source synthesis and verification flows. Christian loves the idea of all the great open-source tools being interoperable, therfore creating a very powerful ecosystem. This is one of the reasons for him to co-organize this tasty workshop.
Project outline
The workshop chair opens the workshop, welcomes speakers and the audience, provides some information on the workshop, and pitches the posters to be presented in the poster session.
Daniel Grosse
Full professor at Johannes Kepler University Linz & DFKI Bremen
Daniel Große is a full professor at the Johannes Kepler University Linz, Austria, where he is the head of the Institute for Complex Systems as well as the head of the “LIT Secure and Correct Systems Lab” since 2022. His current research interests include verification, virtual prototyping, debugging, synthesis and RISC-V. He published over 160 papers in peer-reviewed journals and conferences in the above areas. He received best paper awards (FDL 2007, DVCon Europe 2018, ICCAD 2018, FDL 2020 and FDL 2022) as well as business-related awards (IKT Innovativ Award 2013, Weconomy Award 2013, and Embedded Award 2014). He is an IEEE Senior Member and an Allied Member of the Accellera Systems Initiative in the SystemC Verification Working Group.
Francesco Gonnella
Senior Firmware Engineer at University of Birmingham
Francesco’s main fields of expertise are high-energy physics detectors and trigger/data-acquisition systems, with particular interest in digital electronics and FPGA programming. He has worked as a Research Fellow in Frascati, in the NA62 experiment at CERN, mainly focusing on electronics and data-acquisition. Within this period he spent 18 months at CERN and served as run coordinator during the first NA62 physics run. Since the end of 2015, he has been working in the University of Birmingham Particle Physics group In ATLAS Francesco is responsible for firmware development in phase-1 and phase-2 upgrades In DUNE Francesco is involved in the developing of the data acquisition system for the far detector. In NA62 Francesco in responsible for the trigger system of 2 detectors (RICH and large-angle photon vetoes) and developed many systems used in the NA62 data acquisition. He covered several positions of responsibility such as: Run coordinator, on-call expert for many systems.
Project outline
Hog is a set of Tcl/Shell scripts plus a suitable methodology to handle HDL designs in a Git repository. Hog guarantees firmware synthesis with Place and Route reproducibility and assuring traceability of binary files by exploiting advanced Git features and integrating itself with HDL IDEs: Xilinx Vivado, Xilinx ISE, Intel Quartus, Microchip Libero to reduce as much as possible useless overhead work for the developers.
Lucas Klemmer
PhD Student at Johannes Kepler University Linz
Lucas Klemmer is a PhD student at the Institute for Complex Systems at the Johannes Kepler University in Linz, Austria. He received his Master’s degree in computer science from the University of Bremen in Germany. Currently, his research interest include RISC-V, verification at the HW/SW interface, and new EDA approaches.
Project outline
RISC-V’s growing traction leads to the release of new RISC-V cores on a near monthly basis. In this growing and diverse ecosystem, understanding the performance and other properties of a RISC-V core is of great importance since selecting the best fitting core is mandatory for a successful project. Analyzing RISC-V cores by hand is not possible due to the ever-increasing number of available cores and available software benchmarks might not be fine-grained enough to understand a core completely. Programming and powerful programming languages have proven to provide the productivity that is required to keep pace with these fast developments. In this paper we present a case study1 in which we use the Domain Specific Language WAWK to analyze the performance of all instructions of SERV, a well known bit-serial RISC-V core. With WAWK, only a few lines of code are necessary to calculate the respective metric on the waveform generated during simulation.
Oscar Gustafsson
Associate Professor at Linköping University
Dr. Gustafsson received his MSc and PhD degrees in 1998 and 2003, respectively, both from Linköping University, Sweden. He is currently the head of the division of computer engineering, at the department of electrical engineering at the same university. His research interests lies in the intersection of signal processing algorithms and hardware implementation.
Stefan Riesenberger
Master Student at TU Wien (Vienna University of Technology)
Stefan is a master student at TU Wien interested in microcontroller programming and FPGA hardware design. Currently exploring power estimation on the Lattice iCE40 FPGA platform.
Project outline
The project wants to provide generic micro benchmarks to characterize power use of target technologies. Measured power results will allow to establish power models.
Vamsi Vytla
Electronics Engineer at Lawrence Berkeley National Lab
Vamsi Vytla, is an Electronics and Software engineer, with experience in Research and Industry developing performant FPGA and software designs
Project outline
Newad is a register map automation tool for Verilog.