Call for papers
There is no doubt that proprietary EDA tools are successful, mature, and fundamental for hardware development. However, the “walled garden” approach created by closed-source tool flows can hamper novel FPGA/ASIC-based applications and EDA innovation alike by requiring that researchers either operate within the limits of what has already been imagined, or require that they attempt to simulate their effects on incomplete models, potentially leading to incorrect conclusions.
Another recent development has been growing activity in the open-source community to produce open equivalents of EDA tools, as well as efforts to document FPGA architectures. For instance, Yosys has been widely used for behavioral synthesis since 2012 and Project Icestorm, the first fully open-source FPGA design flow has been available since 2015; together they enabled Trenz Electronic’s icoBOARD, a Raspberry Pi accessory that could be programmed entirely using its ARM CPU, a platform not otherwise supported by the vendor. The availability of low-cost FPGA development boards such as the icoBOARD, TinyFPGA, IceZUM Alhambra, the iceBreaker board, amongst others have also played a part in fostering this “Open FPGA” movement. With OpenLANE and the Skywater process development kit, an open-source tool flow emerged that synthesizes RTL models to GDSII, gracefully enabling open-source ASIC design. The advantages of open design automation -- as Linux has provided for operating systems -- are many: unrestricted research and development, improved quality due to competition, teaching benefits, as well as lowering the barrier and risk to entry, and time to market, of start-ups for building novel applications, tools, and silicon. With such an open-source ecosystem in place, ASICs and reprogrammable logic could achieve the same success and inspire the next generation of hardware engineers as the Raspberry Pi has done for software engineers.
OSDA intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and re-usability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field -- particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions -- standalone technology that would not normally be regarded as novel by traditional conferences -- such that others inside and outside of academia may build upon it.
Topics
We request contributions of the following topics, including but not limited to:
- Open-source EDA tools -- the latest developments, breakthroughs, challenges and surveys on the toolflows required to target real silicon parts: synthesis, verification, place and route, etc.
- Open-source IP -- contributions that enrich the IP ecosystem and reduce the need to “re-invent the wheel”, e.g. PCIe and DDR controllers, debug infrastructure, etc.
- Design methodologies provided as open-source -- such as hardware description languages (e.g. MyHDL, Chisel), domain specific (DSL), high level synthesis (HLS), or asynchronous methods.
- Directions on where the open-source EDA movement should go, current weaknesses in the toolchain, and/or perspectives from industry on how open-source can affect aspects of safety, security, verification, IP protection, time-to-market, datacenter/cloud infrastructure, etc.
- Discussions and case studies on how to license, acquire funding, and commercialize technologies surrounding open-source hardware, which may be different to open software.
Important Dates
Thank you to all authors who already submitted a paper manuscript by the original deadline! We appreciate very much the efforts you put into your work by meeting the very tough deadline! Due to many requests, we decided to extend the deadline to a decent day after the holidays. We hope this helps you preparing your manuscript for submission!
| Event | Date |
|---|---|
| Submission Deadline | |
| Notification | |
| Camera-ready final version | |
| Workshop | April 17, 2023, 14:00--18:00 (2PM--6PM) |
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Submission instructions
Prospective authors are invited to submit original contributions (up to six pages), extended abstracts describing work-in-progress or position papers (not exceeding two pages), and demo proposals that would be of general interest. Papers must be submitted as an A4-sized PDF, in the IEEE conference format.
In line with OSDA’s mission, we encourage and will favour submissions that make all artifacts used for experimentation (benchmarks, code, etc.) available for private peer-review. Accepted submissions are required to publish these artifacts under an OSI-approved (preferably permissive) license.
The proceedings of this workshop containing all accepted papers will be published on the open-access arXiv repository. Every accepted paper must have at least one author registered to attend the workshop by January 31 March 16, 2023. Selected papers may also be considered for a special-issue journal.
Please submit your manuscript at our easychair instance:
Paper submission closed. Thank you for submitting your paper!
Program committee
- Andrea Borga, oliscience, Netherlands
- Xin Fang, Qualcomm, USA
- Steve Hoover, Redwood EDA, USA
- Mieszko Lis, University of British Columbia, Canada
- Steffen Reith, RheinMain University of Applied Sciences, Germany
- Nima Taherinejad, University of Heidelberg, Germany
- Claire Xenia Wolf, YosysHQ, Austria
When
OSDA 2023 will take place on April 17, 2023, 14:00--18:00 (2PM--6PM), and will be co-hosted with the Design, Automation and Test in Europe (DATE) Conference.
Where
OSDA 2023 will happen at the Flanders Meeting and Convention Center Antwerp (FMCCA) in Antwerp, Belgium