The workshop chair opens the virtual workshop, welcomes our speakers and our audience, and provides some information on the workshop.

RustHDL is an open source framework in which the Rust programming language is repurposed for describing hardware. It aims to bring the benefits of the Rust programming language to the task of firmware design, and focuses on enabling the use of features such as strong typing, ease of design reuse, and rigorous safety and linting in the implementation of firmware. RustHDL has a fairly extensive library of IP cores for common hardware tasks, and has been fielded in commercial systems. This paper describes the core concepts of RustHDL, and the lessons learned from the initial releases.

For efficient design, verification and validation of integrated circuits and components is critical. It is also important to have an adaptable and extendable workflow in the rapidly advancing field of silicon photonics. Due to the steadily increasing amount of components within a single circuit, a highly efficient workflow for designing functional building blocks, placing them within a layout and automatically interconnecting them becomes necessary for creating state-of-art circuitry. Furthermore, to allow for highly complex circuits, a hierarchical approach needs to be pursued, in which simple, rigorously simulatable components can successively be composed into larger components, which can be understood based on circuit-level simulations. For characterization of both, the simple components and complex compositions, efficiently usable flows for simulations and measurements need to be provided. In response to this need, we present gdsfactory, a powerful Python library designed to facilitate the creation of integrated circuits for photonics, analog, quantum, MEMS, and more. Gdsfactory offers a unified syntax that seamlessly integrates design, simulation, verification, and validation. This work describes the extensive capabilities of the library, highlighting its end-to-end workflow. We show how gdsfactory enables users to transform their chip designs into validated products, supporting efficiency and precision in silicon photonics design. GDSFactory has been used in educational context to teach silicon photonic design, notably in the UBCx course “Silicon Photonics Design, Fabrication and Data Analysis” taught by Prof. Lukas Chrostowski and for Princeton University’s “ECE559: Photonic Systems” course taught by Prof. Paul Prucnal.

APyTypes is a new Python library, written in C++, that provides scalars and multi-dimensional arrays with configurable fixed- and floating-point representations. It is suitable for finite word-length design exploration and to provide reference data for custom hardware implementations.

We build a new translation from Calyx, an open-source intermediate language for compiling high-level programs into hardware accelerators, to FIRRTL, an intermediate representation used in the open-source Chisel and CIRCT projects. Calyx previously targeted Verilog as a de facto intermediate language for hardware description; our new backend avoids the complexity of targeting Verilog source code and requires important generalizations for the Calyx compiler. We demonstrate the technical challenges endemic to bridging high-level and low-level hardware compiler infrastructures.

Thermal analysis is crucial for designing computing systems alongside their cooling mechanisms. However, existing tools face challenges in addressing large-scale problems and long simulation times. PACT is a SPICE-based parallel thermal simulator capable of fast and accurate simulations from standard-cell to architecture levels. PACT leverages multicore processing and various solvers and can be easily extended to model a variety of cooling and integration technologies. Compared to state-of-the-art tools like COMSOL and HotSpot, PACT offers significant speedups while maintaining accuracy.