Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at UC San Diego. He was visiting scientist at Cadence (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a fellow of ACM and IEEE. He was the 2019 Ho-Am Prize laureate in Engineering. He has served as general chair of DAC, ISPD and other conferences, and from 2000-2016 served as international chair/co-chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers working groups. He is principal investigator of “OpenROAD” https://theopenroadproject.org/, and principal investigator / director of “TILOS” (The Institute for Learning-enabled Optimization at Scale, https://tilos.ai/), an NSF AI Research Institute.

Dr. Antonino Tumeo received the M.S degree in Informatic Engineering, in 2005, and the Ph.D degree in Computer Engineering, in 2009, from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in the PNNL's High Performance Computing group. He Joined PNNL in 2009 as a post doctoral research associate. Previously, he was a post doctoral researcher at Politecnico di Milano. His research interests are modeling and simulation of high performance architectures, hardware-software codesign, FPGA prototyping and GPGPU computing.

Claire Xenia Wolf is co-founder and CTO of YosysHQ, a company focusing on formal hardware verification and advancing Open Source EDA tools. She is best known for her numerous Open Source projects, including Yosys, SymbiYosys, Project IceStorm, Project X-Ray, riscv-formal, PicoRV32, and OpenSCAD. Claire was vice-chair of the RISC-V BitManip Task Group and author of the RISC-V BitManip spec document. In December 2020 she was awarded that year's RISC-V Board of Directors Technical Leadership Award in recognition of her contributions and leadership in the bit manipulation task group (that she co-chaired) and her active role in various other RISC-V technical groups. When she is not tinkering with RISC-V or Open Source EDA, Claire is playing Go/Baduk/Weiqi online, or is playing comically bad Golf offline

Frans received a M.S degree in Computer Engineering from Linköping university in 2019 and is now a PhD student, also at Linköping University. His primary research interest is developing better tools for programming FPGAs. His main project is the Spade HDL, and before working on that his primary research project was Cinnabar, a HLS tool for simulation models.

Jean-Paul Chaput holds a Master Degree in MicroElectronics and Software Engineering. He joined the LIP6 laboratory within SU (formerly UPMC) in 2000. Currently he is a Research Engineer in the Analog and Mixed Signal Team at LIP6. His main focus is on physical level design software. He is a key contributor in developing and maintaining the Alliance/Coriolis VLSI CAD projects for CMOS technologies. In particular he contributed in developing the routers of both Alliance/Coriolis and the whole Coriolis toolchain infrastructure. He his now a key contributor in extending Alliance/Coriolis to the Analog Mixed-Signal integration for nanometric CMOS technologies. He is fully commited to the Open Hardware approach.

Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft. Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.

Larry Doolittle is a Senior Scientist/Engineer at Lawrence Berkeley National Laboratory (it's in Berkeley, not Livermore), with degrees in Engineering and Materials Science. He has spent the last two decades pushing performance boundaries of RF instrumentation and control for particle accelerators, with DSP-in-FPGA as an enabling technology. A culture of collaboration has drawn him to OSDA, and he has contributed to many such projects. Since 2005, he has led development and maintenance of vhd2vl, a tool that can help Verilog and VHDL programmers collaborate smoothly. He is a strong proponent of portable, vendor-neutral HDL designs.

Matthew Guthaus is a Professor in Computer Science and Engineering at the University of California Santa Cruz. He received his BSE in Computer Engineering and MSE and PhD in Electrical Engineering, all from The University of Michigan. Prof. Guthaus is a Senior Member of ACM and IEEE and a member of IFIP Working Group 10.5. His research interests are in low-power computing and electronic computer-aided design including new circuits, architectures, algorithms, and software to address challenges in modern design flows. Dr. Guthaus is the creator of the OpenRAM memory compiler and has interests in open-source computer-aided design and design flows. Dr. Guthaus is the recipient of a 2011 NSF CAREER award, a 2010 ACM SIGDA Distinguished Service Award, and a 2019 Google Faculty Research Award.

Myrtle is a PhD student at Heidelberg University, who maintains the open source nextpnr FPGA place-and-route toolchain as well as the FABulous eFPGA generation framework. They are currently working on finding ways of improving application specific eFPGAs by tightly integrating the fabric generator and the toolchain.

Rishiyur Nikhil studied at IIT Kanpur (Bachelor's) and U. Pennsylvania (PhD). He was a faculty member in MIT's Lab for Computer Science, researching functional programming languages, dataflow and multithreaded computer architectures, and fine-grain MIMD parallelism, continuing this work at Digital Equipment Corp.'s Cambridge Research Lab. In the early 2000s he co-founded Bluespec, Inc., and remains CTO, working on the BSV and BH High-Level Hardware Design Languages, their tools and applications. He has created several open-source RISC-V CPU and System designs, and chaired the RISC-V Foundation's technical group that developed the RISC-V ISA formal spec.

Tim Edwards is a long-time advocate of open source hardware and the open source tools to create it. He maintains magic, netgen, xcircuit, IRSIM, qflow, and others, and regularly contributes to open source EDA tool development. He helped develop the first open-source PDK from SkyWater, the Efabless open MPW shuttle run, and the Efabless Caravel harness chip. He spends much of his time on Slack helping designers get their open source chip designs done.

Tristan Gingold has developed GHDL for more than 20 years as a hobby project. He mainly works on embedded developments, low level software and digital designs.

Dr. Huang is an assistant professor in the ECE Department at the University of Utah. He received his PhD from the ECE Department at the University of Illinois at Urbana-Champaign and BS/MS from the CS Department at Taiwan's National Cheng Kung University. His research group has been creating software systems to streamline the building of high-performance computing (HPC) applications, including ML, CAD, and quantum computing. Dr. Huang receives several awards for his research contributions, including ACM SIGDA Outstanding PhD Dissertation Award, NSF CAREER Award, and Humboldt Research Fellowship Award.