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WSVA: A SystemVerilog Assertion to WAL Compiler

Lucas Klemmer and Daniel Grosse


SystemVerilog Assertions (SVA) is an industry stan- dard for specifying properties that describe the correct behavior of a system. Compared to SystemVerilog’s immediate assertions, they provide a much more powerful syntax including expressing properties spanning over multiple clock cycles. However, to the best of our knowledge, SVA is not supported by any available open-source Electronic Design Automation (EDA) tools. In this paper, we present WSVA, a compiler from SVA to the Waveform Analysis Language (WAL).